1. Field of the Invention
The present invention is generally in the field of electrical circuits and systems. More specifically, the present invention is in the field of memory systems and devices.
2. Background Art
In various memory devices, such as RAMs (random access memory), CAMs (content addressable memory), or other memory devices, that handle a large amount of input data, the number of inputs to the memory device need be managed and reduced to, for example, reduce problems associated with data routing when there are numerous input pins. Moreover, in applications where the write operation throughput is not as important or critical as throughput of other memory device operations, such as read or compare operations, it is beneficial to be able to interrupt the write operation while performing a number of other operations so that system throughput is in effect increased.
However, various problems are encountered when there is an attempt to reduce the number of inputs by spreading a write operation across more than one cycle, e.g. when performing a multi-cycle write operation. One such problem is that while providing for a multi-cycle write operation in effect results in a two-to-one reduction of inputs to a write block of a memory device, interrupting the write operation mid-way, i.e. after passage of only one cycle, could result in corrupt data, i.e. invalid data, being provided to the memory array.
Thus, it is desirable to reduce the number of inputs to a write block in a memory device, such as a RAM or a CAM, by performing a multi-cycle or a multi-cycle write operation, while being able to interrupt the write operation without writing corrupt or invalid data into the memory device.